1109 Wunderlich Dr. San Jose, CA 95129
Voice: (408) 996-9460
Fax: (408) 996-3960
Email: richard@wheeler.com


  • Consultant to mid and senior level management regarding CMOS design, signal integrity and VLSI packaging. Assists in organizing new departments. Provides training for engineers regarding signal integrity. Helps debug problems to get a product out sooner.
PROFESSIONAL SUMMARY: Management consultant since 1996.

Over 26 years experience in industrial management, research, and hardware development, including:

    • Highly effective manager.  Tasks and results oriented.  Able to make tough decisions.
    • Ability to recruit, select and retain the best people.  Committed to enhancing the personal and professional development of subordinates.
    • Employee 5 in startup company, managing R&D activity.
    • Technology design of high speed super computers, mainframes and workstations.
    • Bipolar and CMOS process and equipment design.
    • High-speed networking: physical layer and OS interface.
    • Key strengths are management and design for highest performance, hardware prototyping and development, and broad technical expertise.
    • Authored 14 patents and a technical paper.
    • Ph.D. in E.E. and Solid State Physics.
Hardware: Unix Workstations (HP, Sun), PC, Macintosh
Languages: Quick Basic, Fortran, Excel Macro, Mathematica, Visual Basic
Software: SPICE (Meta, Berkeley, Intusoft, HP), Claris Draw, MS Word, Excel, Power Point
  • Hewlett Packard
  • Management consultant to Computer Technology Lab.  Evaluated multi-divisional VLSI packaging program for future computer products and recommended cost saving alternatives.  HP will save $10M - 100M in development and component costs by implementing my recommendations.
  • VLSI Technologies, Inc. Management consultant to the Technology Division. Defined the framework to build a new VLSI packaging department and interviewed candidates for the director and engineer positions. Trained technical contributors in high performance packaging technology and invented a new technique for chip to solder bump redistribution that was filed in a patent disclosure. Acted as technical advisor to a  multi-divisional council responsible for coordinating flip chip development procedures across company boundaries. Acting as technical advisor to the Network Division to design CMOS driver/receiver circuits capable of operating greater than 1000 MHz.
  • ATL Technologies
  • Bay Microsystems
  • Fujitsu Computer Packaging Technologies
  • Hal Computer
  • Integral Wave Technologies
  • Intel
  • Lantern Communications
  • Nexsi
  • Nvidia
  • Sun Microsystems
  • Sonic Wall
  • Transmeta
  • Managed the first phase of a high performance-networking project.  Increased throughput by a factor of 5 that allowed customers to retain old systems despite increases in network size.
  • There was a need to design a CMOS switching test chip because CPU chips have limited BUS switching capability caused by inductance in the power supply .  Successfully overcame problems of no budget and no staff.  Created a design that allowed clocking 0.5 micron devices at 1000 instead of 250 MHz.  The chip design, layout, and fab were finished in just 15 weeks, exceptional turn around for a custom CMOS.
  • Memory chips are small,  but the package that holds them together is usually 100 times larger.  Invented a low cost, three-dimensional package for DRAM.  Was granted a patent for successfully using the chip edge for connection.  The concept has been tested and demonstrated to upper management.
  • LICA capacitors are the lowest inductance surface mount capacitors available but are ineffective at frequencies above 100 MHz.  Devised a simple method to reduce the inductance by 3 enabling computer manufacturers to lower the cost of computers by using fewer LICA capacitors.
  • Served as the principal architect and designer of an exploratory 200 megabits per second network that coexisted with a 10Mbs. Ethernet CSMA/CD network.  Invented an adaptive equalizer technique in the receiver that allowed random distances between nodes in the network.  Designed, built and successfully tested the system.
Manager, Packaging R&D Department
    • As employee number 5 in this start up company, selected to manage both the Mechanical Systems Department and the Electrical Systems Department.
    • As a start up, Fujitsu Computer Packaging Technologies had no computers, telephones, or network connections.  Designed the technical infrastructure, negotiated all contracts, supervised the installation and debugging of all systems, and managed the MIS function.
    • Built the Electrical Systems Department and measurement laboratory from scratch.
    • Responsible for goals, deliverables, schedules, interfacing with customers, hiring, performance evaluations for both departments, and departmental budgeting.
    • Chaired the Safety and ESD committees and am a member of  the Emergency Response Team, with a First Aid specialty.
    • Played a key role in inventing a new type of interconnect between VLSI chips and PC boards.  The new interconnect will allow computer CPUs to operate at clock frequencies above 1000 MHz.  Led my department in developing the tools to predict and measure the hardware performance.  Submitted thirteen patent disclosures to the patent office relating to high speed interconnect.
    • Created a low cost, stable standard to calibrate my oscillators and counters in my calibration lab.  The Cesium frequency standard costs about $60,000.  Purchased a GPS navigation receiver and a used crystal oscillator to create a system with the accuracy of the Cesium standard for less than $2,000.
Project Manager
    • Managed the advanced packaging team in the Super Workstation (SWS) program.  Responsible for hiring and technically leading a team that developed the electrical interconnect for a high speed computer workstation product that would allow clock frequencies of 500 MHz.
    • Also coordinated the packaging efforts of Apollo and CTG R&D divisions and coordinated the efforts to find technology vendors outside HP with respect to the SWS program.
    • Obtained two patents with a third still pending.
Program Manager, High Speed Network Foundation
    • Managed the program in the Network Architecture Lab.  Program team consisted of 12 engineers and 2 project managers and spanned 4 lab boundaries, drawing members from NAL, IND, RND, and HP Labs/England.
    • Defined and obtained approval for the program charter and to build and direct the team. Directed the program to the completion of phase 1, the most difficult phase of a three phase program, which resulted in a 5 times increase in networking throughput compared to current products.
    • Trained a successor who managed the final 6 months of the program when I returned to HP Labs.
Chief Engineer
    • Specified the technology and packaging necessary to build a bipolar RISC architecture computer.  The task included selecting a gate array vendor and specifying the electrical design rules, clock distribution methodology and critical path delay equations.  I have extensive experience using SPICE and other circuit simulation programs.
    • Served as principal architect and designer of an exploratory 200 megabits per second data communications network that coexisted with a prototype 10Mbs. ETHERNET CSMA/CD coaxial cable network.  Invented an adaptive equalizer technique in the receiver to allow random distances between nodes in the network.
    • Designed and constructed a low power 560 MHz. local oscillator chain and IF amplifier strip for a Global Position Satellite navigational receiver using Surface Acoustic Wave  resonators.  Also designed UHF antennas, low noise amplifiers, mixers and oscillators to 3 GHz.
    • Principle designer for an advanced digital to analog deflection amplifier system for use in a prototype electron beam lithographic system.  Invented the instrumentation necessary to measure the settling time and calibrate the deflection accuracy of the amplifier in situ.  Met with NBS and other manufacturers to initiate standards of measurement for high performance DACs.
    • Did extensive device and circuit design, modeling, and determination of design rules for three new IC families.  Designed 3 functioning ICs in advance NMOS and CMOS processes.  Designed analog and digital circuits using discrete TTL, NMOS, CMOS and 10K-100K ECL technologies.
    • Researchers at HP developed a theory for deflecting electron beams using electrostatic deflection rather than magnetic circuits.  Because none existed, designed the test equipment that measured amplifier performance.  Three E-Beam mask makers were built and used in R & D and manufacturing, had better performance and accuracy than any machine on the market, and gave HP a leadership position in the field.
    • Crystal oscillators are cost effective from 1 to 100 MHz.  The local oscillator for a global positioning system receiver needed to operate at 560 MHz.  Designed a low power oscillator using a SAW resonator.  The cost was reduced by 4, and the power was reduced by 100, for the same accuracy.  A working prototype was built, tested, and met all goals.  Executive management decided to sell the technology to Trimble Navigation that has since become the leader in GPS technology.
Member of the Technical Staff,
Exploratory Data Development Department
Project engineer in charge of designing a data set that allowed interfacing computer graphics to a PICTUREPHONE.
  • Purchased and installed computer and telecommunications components, and wrote the software to remote sense lights, heat, water and human presence throughout a cabin 150 miles from my home in San Jose.  From my computer in San Jose, can remotely turn cabin lights and utilities on or off and watch snow falling on the cabin's back deck.
  • Designed a microwave receiver that has a local oscillator operating between 1000 and 3000 MHz. Invented a way to combine a divide by 64 and a divide by 125 counter to obtain a divide by 1000.  The output of the divider circuit is exactly 1000 lower in frequency than the input to the counter that is now used constantly with my receiver.
EDUCATION: Ph.D., Brigham Young University, Provo, UT.  E.E. department with focus on Solid State Physics.
Dissertation subject: Electrical, Mechanical, and Thermal Properties of Synthetic Polycrystalline Diamond.
National Science Foundation Fellowship.

M.S.E.E., Stanford University, Stanford, CA.  Focus on Solid State Electronics
Bell Telephone Labs OYOC fellowship.

B.E.S., Brigham Young University, Provo, UT.
Graduated Cum Laude second in class of 32.

  • Driver/Receiver Pair for low noise digital signaling,  Patent #4,987,322
  • High-Speed High Density Chip Mounting,  Patent #5,113,314
  • Time-Domain Skin-Effect Model for Transient Analysis of Lossy Transmission Lines.  Proceedings of the IEEE, VOL. 70, JULY 1982, pp750-757.


  • On-Chip Capacitance for Suppressing switching Noise
  • Special Interconnect Layer for Advanced Multi-Chip Module Packages
  • A Process for Fabricating a Substrate with Thin Film Capacitor and Insulating Plug
  • Wire Heat Sinks on the Backside of Chips
  • Power Supply Distribution Structure for Multichip Modules and Method for Making Same
  • Constant Power Consumption of CMOS IC Chips
  • Electrical Connector Using a Remelting Solder
  • A Technique to Fabricate Large Chip Capacitors With High Yield
  • Novel Resistance, Capacitor Plate Structure
  • A SPICE Compatible Circuit to Model Skin Effect of Conductors Both in Frequency and Time Domain
  • A SPICE Implementation of Ideal Transformer Valid from DC to Infinite Frequency Range
  • Pre-tested Capacitor That is Stable at High Temperatures