Modeling Simultaneous Switching Noise (SSO) in the Z-axis Direction of VLSI Packages and PCB’s.

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Table of Contents

Modeling Simultaneous Switching Noise (SSO) in the Z-axis Direction of VLSI Packages and PCB’s.

Topics:

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Maximum Coupling Length

Critical Lengths for 100 pS Risetime

Amount of Crosstalk

Design 1 - Good Design

Design 2 - Still Good Design

Design 3 - Much more coupling

Design 4 - Thicker Metal

Design 5 - Remove one Ground

Design 6 - Holes in Ground

Design 7 - Circular Conductors

Critical Lengths for 100 pS Risetime

How long are they?

“Hey Buddy! You’ve got your directions mixed up.”

Vias Through Ground Planes

Equivalent Circuit - No Planes

What to Do?

Make each layer thin

Reduce Er

Examine Signal Patterns

Pattern 1 - 3:1 Chevron 

Pattern 1 - 3:1 Chevron

Pattern 2 - 3:1 Checker Board

Pattern 2 - 3:1 Checker Board

Pattern 3 - 1:1 Checker Board

Pattern 3 - 1:1 Checker Board

Inside Package - 1:4 Pattern

Practical Experience

5x5 Array Example

5x5 Array Example

Equivalent Circuit

Wave / Particle Duality

Speedup Trick

Conclusions:

Vias Through Power & Ground

Author: Richard Wheeler

Email: richard@wheeler.com

Home Page: http://www.wheeler.com

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