Conclusions
.25 micron CMOS requires 3D package modeling
- Limited noise margins
- Lower power supply voltages
- Higher power supply currents
- More internal gates switching
- Thousand I/O's
On-chip is the best place to put bypass capacitance
Buried substrate capacitance is needed for ASIC chips
Surface mount capacitors have limited effectiveness at 0.25 micron CMOS
Power connectors are becoming more important
Systems houses are looking to package vendors to supply performance guidelines