Wheeler Enterprises Brochure

Objective:

Consultant to mid and senior level management regarding CMOS design, signal integrity and VLSI packaging

• Assists in organizing new departments
• Provides training for engineers regarding signal integrity
• Helps debug problems to get a product out sooner

Summary of Services: - Specialize in 10 GHz technology

• Strategic Planning
• Technical Training
• Signal Integrity
• Transmission Lines
• CMOS I/O Driver, Receiver design
• VLSI Package Design

Description of Services:

• Strategic planning
  • Helping create new departments
    • Planning the organization's structure
    • Finding and interviewing engineers
    • Acquiring necessary equipment
  • Recommending resource allocation and budgeting for design projects
• Technical Training
  • Short presentations
    • High speed CMOS Design
    • Signal Integrity and noise margins
    • Power supply design
    • VLSI packaging tradeoffs
    • Simultaneous switching (NSSO) noise
• Signal Integrity
  • Decoupling bypass capacitors
  • SPICE models for vias, bends, crossovers, etc.
  • SPICE models for surface mount bypass capacitors
  • Simulation of connectors and interconnects
  • Signal termination methodologies
  • Differential clocks and data
  • Power distribution plane models, (split planes)
  • Delta-I-Noise and Ground bounce
  • Simultaneous switching noise suppression
  • Interconnects and testing
  • Measurements and modeling
  • Propagation Characteristics and parameter extraction
  • Inter-symbol Interference
  • Backplane analysis
• Transmission Lines
  • Stripline, Microstrip, Coplanar, Twisted pair, Differential lines
  • Impedance, Delay, Crosstalk, SPICE skin-effect loss models
  • Series, shunt, active termination
  • 2D field solver (RLCG Matrix)
  • Delay lines
  • Long cables
  • Guard traces for shielding
• CMOS I/O Driver, Receiver design
  • HSTL, SSTL, LVDS, USB, Misc. (4 Gb/S)
  • Differential cable driver - receivers
  • Bus design and modeling
  • Source asynchronous clocking
  • Common mode noise rejection
  • 8B/10B codes to reduce inter-symbol interference
  • Analog and digital equalization techniques
  • Clock distribution - skew and jitter reduction
  • Clock PLLs and DLLs
• VLSI Package Design - Single chip and MCMs
  • Specialize in the design of organic flip chip VLSI packages
    • 1) PTFE, 2) buildup, 3) tape packages
    • 10 GHz. clock frequency
    • 20 - 500 Pico second risetimes
    • 500 - 2200 I/O's
    • Controlled impedance
    • Internal bypass capacitors
    • 10-200 Watts
  • Ball Grid Array (BGA) packages
  • Area array sockets
  • Package and socket electrical characterization

References:

• ATL Technologies
• Bay Microsystems
• Fujitsu Computer Packaging Technologies
• Hal Computer
• Hewlett Packard
• Integral Wave Technologies
• Intel
• Intrinsity
• Lantern Communications
• Nexsi
• Nvidia
• Sun Microsystems
• Sonic Wall
• Transmeta
• VLSI Technologies

How to contact:

Dr. Richard L. Wheeler
1109 Wunderlich Dr. San Jose, CA 95129
Voice: (408) 996-9460
Fax: (408) 996-3960
Email: richard@wheeler.com